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1 pf1245-01 micro mini s1c60n08/60r08 4-bit single chip microcomputer s1c6200c core cpu built-in lcd driver serial interface description the s1c60n08 series is a single-chip microcomputer made up of the 4-bit core cpu s1c6200c, rom (4,096 words 12 bits), ram (832 words 4 bits), lcd driver, serial interface, event counter with dial input function, watchdog timer, and two types of time base counter. because of its low-voltage operation and low power consump- tion, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. the s1c60r08 is a microcomputer with a cmos 4-bit core cpu s1c6200c as main component, and a built-in programmable ram (rom emulator). the s1c60r08 has almost the same functions as the s1c60n08/60a08. the mask rom in the s1c60n08/60a08 has been changed to a rom emulator that allows the user to rewrite programs using a serial eeprom. configulation the s1c60n08 series is configured as follows, depending on supply voltage and oscillation circuits. model supply voltage oscillation circuit evaluation tool s1c60n08 3.0 v osc1 only (single clock) s1c60r08 S1C60A08 3.0 v osc1 and osc3 (twin clock) s1c60l08 1.5 v osc1 only (single clock) features osc1 oscillation circuit ................... crystal oscillation circuit 32.768 khz (typ.)/38.400 khz (typ.) osc3 oscillation circuit ................... cr or ceramic oscillation circuit ( ? 1) 500 khz (typ.) ... S1C60A08/60r08 only instructi on set .................................. 108 types instruction execution time ............... clk = 32.768 khz: 153 ?ec, 214 ?ec, 366 ?ec (differs depending on instruction) clk = 38.400 khz: 130 ?ec, 182 ?ec, 313 ?ec (clk: cpu operation frequency) clk = 500 khz: 10 ?ec, 14 ?ec, 24 ?ec... S1C60A08/60r08 only rom capacity ................................. 4,096 words 12 bits serial eeprom interface ............... bu ilt-in (microchip 24aa65 two wire bus protocol interfaces ... s1c60r08 only ram capacity .................................. 832 words 4 bits input ports ....................................... 9 bits (pull-down resistor can be added ? 1) output ports .................................... 8 bits (bz, bz, fout and siof outputs are available ? 1) i/o ports .......................................... 8 bits (pull-down resistor is added during input data read-out) serial interface ................................ 1 port (8-bit clock synchronous system) lcd driver ....................................... 48 segments 4, 3, or 2 commons ( ? 1) v-3 v 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) time base counter .......................... two types (timer and stopwatch) watchdog timer ............................... buil t-in ( ? 1) low voltage operation products
2 s1c60n08/60r08 event counter .................................. two 8-bit inputs (dial input evaluation or independent) sound generator ............................. programmable in 8 sounds (8 frequencies) digital envelope built-in ( ? 1) analog comparator .......................... inverted input 1, non-inverted input 1 battery low detection circuit (bld) .. dual system (programmable in 8 values and a fixed value) 2.4 v, 2.2?.55 v ... s1c60n08/60a08/60r08 1.2 v, 1.05?.4 v ... s1c60l08 external interrupt ............................ input interrupt: 3 systems internal interrupt .............................. time base counter interrupt: 2 systems serial interface interrupt: 1 system supply voltage ................................ 3.0 v (1.8?.5 v) ... s1c60n08/60a08/60r08 1.5 v (0.9?.7 v) ... s1c60l08 current consump tion ...................... s1c60n08 halt state: 1.0 ? when clk = 32.768 khz (typ.) run state: 2.2 ? when clk = 32.768 khz (typ.) s1c60l08 halt state: 1.0 ? when clk = 32.768 khz (typ.) run state: 2.2 ? when clk = 32.768 khz (typ.) S1C60A08 halt state: 1.1 ? when clk = 32.768 khz (typ.) run state: 3.0 ? when clk = 32.768 khz (typ.) run state: 50 ? when clk = 500 khz (typ.) s1c60r08 halt state: 1.0 ? when clk = 32.768 khz (typ.) ...target for s1c60n08 1.1 ? when clk = 32.768 khz (typ.) ...target for S1C60A08 run state: 6.5 ? when clk = 32.768 khz (typ.) ...target for s1c60n08 7.5 ? when clk = 32.768 khz (typ.) ...target for S1C60A08 run state: 115 ? when clk = 500 khz (typ.) ...target for S1C60A08 only package .......................................... qfp5-100pin, qfp15-100pin (plastic) or chip ? 1: can be selected with mask option
3 s1c60n08/60r08 block diagram s1c60r08 osc1 osc2 osc3 osc4 ampp ampm com0? seg0?7 v dd v l1 v l2 v l3 ca cb v s1 v ss k00?03, k10 k20?23 test p00?03 p10?13 r00?03 r10?13 otprst reset sin sout sclk errout sda scl core cpu s1c6200c rom emulator 4,096 words 12 bits interrupt generator ram 832 words 4 bits lcd driver 48 seg 4 com power controller osc svd event counter comparator sound generator serial i/f timer stopwatch input port i/o port output port serial eeprom interface system reset control error detecting circuit osc1 osc2 ? osc3 ? osc4 ampp ampm com0? seg0?7 v dd v l1 v l2 v l3 ca cb v s1 v ss k00?03, k10 k20?23 test reset p00?03 p10?13 r00?03 r10?13 sin sout sclk core cpu s1c6200c rom 4,096 words 12 bits system reset control interrupt generator ram 832 words 4 bits lcd driver 48 seg 4 com power controller osc svd event counter comparator sound generator serial i/f timer stopwatch input port i/o port output port s1c60n08/60l08/60a08 ? : S1C60A08 only
4 s1c60n08/60r08 pin configuration s1c60n08/60l08/60a08 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 com1 com0 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 ampp ampm k23 k22 k21 k20 k10 k03 k02 no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg29 seg28 seg27 seg26 seg25 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 k01 k00 sin sout n.c. sclk p03 p02 p01 p00 n.c. n.c. p13 p12 p11 p10 r03 r02 r01 r00 n.c. = no connection no. pin name 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 r12 r11 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb n.c. com3 com2 no. pin name 51 80 31 50 index 30 1 100 81 s1c60n08/60l08/60a08 qfp5-100pin 51 75 26 50 index 25 1 100 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 ampp ampm k23 k22 k21 k20 k10 k03 k02 k01 no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg27 seg26 seg25 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 n.c. seg11 seg10 no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 k00 sin sout n.c. sclk n.c. p03 p02 p01 p00 p13 p12 p11 p10 r03 r02 r01 r00 r12 r11 n.c. = no connection no. pin name 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb n.c. com3 com2 com1 com0 no. pin name s1c60n08/60l08/60a08 qfp15-100pin
5 s1c60n08/60r08 s1c60n08/60l08/60a08 pin description pin name v dd v ss v s1 v l1 v l2 v l3 ca, cb osc1 osc2 osc3 osc4 k00?03 k10 k20?23 p00?03 p10?13 r00?03 r10 r13 r11 r12 sin sout sclk ampp ampm seg0?7 com0? reset test pin no. function power supply pin (+) power supply pin (-) oscillation and internal logic system voltage output pin lcd drive voltage output pin (approx. -1.05 v or 1/2? l2 ) lcd drive voltage output pin (2? l1 or approx. -2.10 v) lcd drive voltage output pin (3? l1 or 3/2? l2 ) boost capacitor connecting pin cryctal oscillation input pin crystal oscillation output pin cr or ceramic oscillation input pin ? (n.c. for s1c60n08 and s1c60l08) cr or ceramic oscillation output pin ? (n.c. for s1c60n08 and s1c60l08) input port pin input port pin input port pin i/o port pin i/o port pin output port pin output port pin or bz output pin ? output port pin or bz output pin ? output port pin or siof output pin ? output port pin or fout output pin ? serial interface data input pin serial interface data output pin serial interface clock input/output pin analog comparator non-inverted input pin analog comparator inverted input pin lcd segment output pin or dc output pin ? lcd common output pin (1/2, 1/3 or 1/4 duty are selectable ? ) initial reset input pin input pin for test qfp5-100 92 85 89 95 94 93 96, 97 91 90 88 87 62?9 58 57?4 70?7 76?3 80?7 83 84 82 81 63 64 66 52 53 51?8, 26? 2, 1, 100, 99 86 27 qfp15-100 90 83 87 93 92 91 94, 95 89 88 86 85 61?8 57 56?3 70?7 74?1 78?5 81 82 80 79 62 63 65 51 52 50?9, 37?6, 24? 100?7 84 25 i/o (i) (i) i o i o i i i i/o i/o o o o o o i o i/o i i o o i i ? can be selected by mask option
6 s1c60n08/60r08 s1c60r08 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 com1 com0 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 ampp ampm k23 k22 k21 k20 k10 k03 k02 no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg29 seg28 seg27 seg26 seg25 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 k01 k00 sin sout otprst sclk p03 p02 p01 p00 scl sda p13 p12 p11 p10 r03 r02 r01 r00 no. pin name 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 r12 r11 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb errout com3 com2 no. pin name 51 80 31 50 index 30 1 100 81 s1c60r08 qfp5-100pin 51 75 26 50 index 25 1 100 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 no. pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 ampp ampm k23 k22 k21 k20 k10 k03 k02 k01 k00 no. pin name 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 seg27 seg26 seg25 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 no. pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 sin sout otprst sclk p03 p02 p01 p00 scl sda p13 p12 p11 p10 r03 r02 r01 r00 r12 r11 no. pin name 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 r10 r13 v ss reset osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb errout com3 com2 com1 com0 no. pin name s1c60r08 qfp15-100pin
7 s1c60n08/60r08 s1c60r08 pin description pin name v dd v ss v s1 v l1 v l2 v l3 ca, cb osc1 osc2 osc3 osc4 k00?03 k10 k20?23 p00?03 p10?13 r00?03 r10 r11 r12 r13 sin sout sclk ampp ampm seg0?7 com0? reset test scl sda errout otprst pin no. function power supply pin (+) power supply pin (-) oscillation and internal logic system voltage output pin lcd drive voltage output pin (approx. -1.05 v or 1/2? l2 ) lcd drive voltage output pin (2? l1 or approx. -2.10 v) lcd drive voltage output pin (3? l1 or 3/2? l2 ) boost capacitor connecting pin crystal oscillation input pin crystal oscillation output pin cr or ceramic oscillation input pin * cr or ceramic oscillation output pin * input port pin input port pin input port pin i/o port pin i/o port pin output port pin output port pin or bz output pin * output port pin or siof output pin * output port pin or fout output pin * output port pin or bz output pin * serial interface data input pin serial interface data output pin serial interface clock input/output pin analog comparator non-inverted input pin analog comparator inverted input pin lcd segment output pin or dc output pin * lcd common output pin (1/2, 1/3 or 1/4 duty are selectable * ) initial reset input pin input pin for test serial eeprom clock output pin serial eeprom data input/output pin errout detecting singnal output for download program cold reset pin for re-start download program from eeprom qfp5-100 92 85 89 95 94 93 96, 97 91 90 88 87 62?9 58 57?4 70?7 76?3 80?7 83 82 81 84 63 64 66 52 53 51?8, 26? 2, 1, 100, 99 86 27 71 72 98 65 qfp15-100 90 83 87 93 92 91 94, 95 89 88 86 85 60?7 56 55?2 68?5 74?1 78?5 81 80 79 82 61 62 64 50 51 49?6, 24? 100?7 84 25 69 70 96 63 i/o (i) (i) i o i o i i i i/o i/o o o o o o i o i/o i i o o i i o i/o o i ? can be selected by mask option
8 s1c60n08/60r08 option list 1. device type ?device type ................................... 1. s1c60n08 (normal type) 2. s1c60l08 (low power type) (note) 3. S1C60A08 (twin clock type) ?clock type (for evaluation board) 1. 32 khz 2. 38 khz 2. osc3 system clock (only for S1C60A08) 1. cr 2. ceramic 3. multiple key entry reset ?combination .................................. 1. not use 2. use k00, k01 3. use k00, k01, k02 4. use k00, k01, k02, k03 ?time authorize ............................. 1. use 2. not use 4. watchdog timer 1. use 2. not use 5. input interrupt noise rejector ?k00?03 ............................................ 1. use 2. not use ? k10 ..................................................... 1. use 2. not use ?k20?23 ............................................ 1. use 2. not use 6. input port pull down resistor ? k00 ..................................................... 1. with resistor 2. gate direct ? k01 ..................................................... 1. with resistor 2. gate direct ? k02 ..................................................... 1. with resistor 2. gate direct ? k03 ..................................................... 1. with resistor 2. gate direct ? k10 ..................................................... 1. with resistor 2. gate direct ? k20 ..................................................... 1. with resistor 2. gate direct ? k21 ..................................................... 1. with resistor 2. gate direct ? k22 ..................................................... 1. with resistor 2. gate direct ? k23 ..................................................... 1. with resistor 2. gate direct 7. output port specification (r00?03) ? r00 ..................................................... 1. complementary 2. pch-opendrain ? r01 ..................................................... 1. complementary 2. pch-opendrain ? r02 ..................................................... 1. complementary 2. pch-opendrain ? r03 ..................................................... 1. complementary 2. pch-opendrain 8. r10 specification ?output specificatio n ............... 1. complementary 2. pch-opendrain ?output type .................................. 1. dc output 2. buzzer output 9. r11 specification ?output specificatio n ............... 1. complementary 2. pch-opendrain ?output type .................................. 1. dc output 2. sio flag 10. r12 specification ?output specificatio n ............... 1. complementary 2. pch-opendrain ?output type .................................. 1. dc output 2. fout 32768 or 38400 [hz] 3. fout 16384 or 19200 [hz] 4. fout 8192 or 9600 [hz] 5. fout 4096 or 4800 [hz] 6. fout 2048 or 2400 [hz] 7. fout 1024 or 1200 [hz] 8. fout 512 or 600 [hz] 9. fout 256 or 300 [hz]
9 s1c60n08/60r08 11. r13 specification ?output specificatio n ............... 1. complementary 2. pch-opendrain ?output type .................................. 1. dc output 2. buzzer inverted output (r13 control) 3. buzzer inverted output (r10 control) 12. i/o port specification ? p00 ..................................................... 1. complementary 2. pch-opendrain ? p01 ..................................................... 1. complementary 2. pch-opendrain ? p02 ..................................................... 1. complementary 2. pch-opendrain ? p03 ..................................................... 1. complementary 2. pch-opendrain ? p10 ..................................................... 1. complementary 2. pch-opendrain ? p11 ..................................................... 1. complementary 2. pch-opendrain ? p12 ..................................................... 1. complementary 2. pch-opendrain ? p13 ..................................................... 1. complementary 2. pch-opendrain 13. sin pull down resistor 1. with resistor 2. gate direct 14. sout specification 1. complementary 2. pch-opendrain 15. sclk specification ?pull down resistor .................. 1. with resistor 2. gate direct ?output specificatio n ............... 1. complementary 2. pch-opendrain ?logic ................................................ 1. positive 2. negative 16. sio data permutation 1. msb first 2. lsb first 17. event counter noise rejector 1. 2048 or 2400 [hz] 2. 256 or 300 [hz] 18. lcd specification ?bias selection s1c60n08 .......................................... 1. 1/3 bias, regulator used, lcd 3 v 2. 1/3 bias, regulator not used, lcd 3 v 3. 1/2 bias, regulator not used, lcd 3 v 4. 1/3 bias, regulator not used, lcd 4.5 v s1c60l08 (note) ............................... 1. 1/3 bias, regulator used, lcd 3 v 2. 1/2 bias, regulator not used, lcd 3 v 3. 1/3 bias, regulator not used, lcd 4.5 v S1C60A08 .......................................... 1. 1/3 bias, regulator used, lcd 3 v 2. 1/3 bias, regulator not used, lcd 3 v 3. 1/2 bias, regulator not used, lcd 3 v 4. 1/3 bias, regulator not used, lcd 4.5 v ?duty selection ............................ 1. 1/4 duty 2. 1/3 duty 3. 1/2 duty 19. segment memory address 1. 0 page (040?6f) 2. 2 page (240?6f) note: the s1c60r08 does not support the s1c60l08.
10 s1c60n08/60r08 s1c60r08 rom emulator/rom emulator programmer the s1c60r08 has a built-in rom emulator, which is constructed by ram, to emulate mask rom. the rom emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read by the cpu. this chapter explain the rom emulator and the programmer circuit. configuration of rom emulator the built-in rom emulator is the same structure with the mask rom built-in s1c60n08. and used for loading the user-program. that has a capacity of 4,096 steps 12 bits. the program area consists of 16 (0?5) pages 256 (00h?fh) steps. after initial reset, the program beginning address is set to bank 0, page 1, step 00h. the interrupt vector is allocated to page 1, steps 01h?fh. step 00h step 0fh step 10h step ffh 12 bits program start address interrupt vector area bank 0 page 0 page 1 page 2 page 3 page 15 step 01h the rom emulator data is downloaded from an external serial eeprom through the programmer circuit. after power on or a high pulse is input to the otprst pin, the rom emulator data is initialized and downloading will be started. configuration of rom emulator programmer the rom emulator data is written through the programmer. the programmer supports data transmit/receive communication with serial eeprom, interface data error check and system reset signal generation. v ss cpu v dd otprst sda scl errout error detect circuit osc1 reset s1c60r08 system reset configuration flag cpu and peripheral circuit rom emulator 4,096 12 bits eeprom interface circuit a2 a1 a0 serial eeprom terminals the programmer uses the following input/output terminals. scl: serial eeprom control clock output terminal sda: serial eeprom data transmit/receive terminal errout: data check result output terminal otprst: data re-loading start input terminal
11 s1c60n08/60r08 operation the s1c60r08 has two operation modes, ?programming mode: load the data from the serial eeprom ?normal mode: work as if the mask rom type the following describes how to operate the s1c60r08. 1) make an application software. 2) convert the software to the serial eeprom format with winedg in the s1c60r08 package. 3) write the program which is converted to the serial eeprom format to the serial eeprom. 4) set up the s1c60r08, the serial eeprom and the other peripheral components on the user target application. (the example is described in "basic external connection diagram".) 5) the application power on. 6) the s1c60r08 enters to the programming mode, and starts data loading from the serial eeprom to the built-in rom emulator automatically. in the loading, internal circuit is kept as system reset condition ex- cept the programmer. and data error checking is done at the same time. 7) if the data error happens, the errout pin goes high level and data loading is terminated. 8) if the data has loaded without any error, the s1c60r08 enters to the normal mode automatically. then the cpu read the rom emulator data as the instruction and start to run as if the mask rom type. 9) if you want to re-load the data, input a high pulse to the otprst pin. then the s1c60r08 enters to programming mode and starts re-loading. summary of notes target type for s1c60n08 series the s1c60n08 has 3 types (s1c60n08, S1C60A08 and s1c60l08). in these models, the s1c60r08 supports the following 2 types as the rom emulator model. s1c60n08 v dd = 3.0 v (typ.), osc1 S1C60A08 v dd = 3.0 v (typ.), osc1/osc3 refer the "s1c60n08/60r08 technical manual". mask/segment option the s1c60r08 can load rom emulator data. but cannot load the mask option and segment option. therefore customer must make the function option data and segment option data by the s1c60r08 development tool at first. then send the data to seiko epson and order the mask. seiko epson makes the s1c60r08 with a customized option according to this request. serial eeprom the external serial eeprom is necessary for programming the rom emulator data, and this component is recommended. recommended component: ak6010a/12a (akm) m24c64/32 (sgs-thomson) br24c64 (rohm) 24aa64 (microchip) note: use larger eeprom than program memory size.
12 s1c60n08/60r08 electrical characteristics absolute maximum ratings s1c60n08/60a08/60r08 rating supply voltage input voltage (1) input voltage (2) permissible total output current ? 1 operating temperature storage temperature soldering temperature / time permissible dissipation ? 2 ( v dd =0v ) symbol v ss v i v iosc i vss topr tstg tsol p d value -5.0 to 0.5 v ss -0.3 to 0.5 v s1 -0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec ( lead section ) 250 unit v v v ma c c mw ? 1: ? 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package. s1c60l08 rating supply voltage input voltage (1) input voltage (2) permissible total output current ? 1 operating temperature storage temperature soldering temperature / time permissible dissipation ? 2 ( v dd =0v ) symbol v ss v i v iosc i vss topr tstg tsol p d value -2.0 to 0.5 v ss -0.3 to 0.5 v s1 -0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec ( lead section ) 250 unit v v v ma c c mw ? 1: ? 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package. recommended operating conditions s1c60n08 condition supply voltage oscillation frequency ( ta=-20 to 70 c ) symbol v ss f osc1 unit v khz khz max. -1.8 typ. -3.0 32.768 38.400 min. -3.5 remark v dd =0v either one is selected s1c60l08 condition supply voltage oscillation frequency ? 1: ? 2: ( ta=-20 to 70 c ) symbol v ss f osc1 unit v v v khz khz max. -1.1 -0.9 ? 2 -1.2 typ. -1.5 -1.5 -1.5 32.768 38.400 min. -1.7 -1.7 -1.7 when switching to heavy load protection mode. the possibility of lcd panel display differs depending on the characteristics of the lcd panel. remark v dd =0v v dd =0v, with software control ? 1 v dd =0v, when analog comparator is used either one is selected S1C60A08/60r08 condition supply voltage oscillation frequency (1) oscillation frequency (2) ( ta=-20 to 70 c ) symbol v ss f osc1 f osc3 unit v khz khz khz max. -2.2 ? 1 600 typ. -3.0 32.768 38.400 500 min. -3.5 50 remark v dd =0v either one is selected duty 50 5%, v ss =-2.2 to -3.5v ? 1: -1.8v when the s1c60r08 is used as the s1c60n08.
13 s1c60n08/60r08 dc characteristics s1c60n08/60a08/60r08 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 unit v v v v a a a a ma ma ma ma a a a a a a max. 0 0 0.8? ss 0.9? ss 0.5 16 100 0 -1.8 -0.9 -3 -3 -200 typ. min. 0.2? ss 0.1? ss v ss v ss 0 4 25 -0.5 6.0 3.0 3 3 200 condition k00?3, k10, k20?3, p00?3, p10?3 sin, (sda) ? 1 sclk, reset, test, (otprst) ? 1 k00?3, k10, k20?3, p00?3, p10?3 sin, (sda) ? 1 sclk, reset, test, (otprst) ? 1 v ih1 =0v k00?3, k10, k20?3, p00?3, p10?3 no pull-down sin, sclk, ampp, ampm (sda) ? 1 v ih2 =0v k00?3, k10, k20?3 with pull-down sin, sclk v ih3 =0v p00?3, p10?3, reset, test with pull-down (otprst) ? 1 v il =v ss k00?3, k10, k20?3, p00?3, p10?3 sin, sclk, ampp, ampm, reset, test (otprst), (sda) ? 1 v oh1 =0.1? ss r10, r11, r13 v oh2 =0.1? ss r00?3, r12, p00?3, p10?3, sout sclk, (sda), (errout), (scl) ? 1 v ol1 =0.9? ss r10, r11, r13 v ol2 =0.9? ss r00?3, r12, p00?3, p10?3, sout sclk, (sda), (errout), (scl) ? 1 v oh3 =-0.05v com0? v ol3 =v l3 +0.05v v oh4 =-0.05v seg0?7 v ol4 =v l3 +0.05v v oh5 =0.1? ss seg0?7 v ol5 =0.9? ss ? 1: ( ) indicate the s1c60r08 pins. s1c60l08 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 unit v v v v a a a a a a a a a a a a a a max. 0 0 0.8? ss 0.9? ss 0.5 10 60 0 -300 -150 -3 -3 -100 typ. min. 0.2? ss 0.1? ss v ss v ss 0 2 12 -0.5 1400 700 3 3 100 condition k00?3, k10, k20?3, p00?3, p10?3 sin sclk, reset, test k00?3, k10, k20?3, p00?3, p10?3 sin sclk, reset, test v ih1 =0v k00?3, k10, k20?3, p00?3, p10?3 no pull-down sin, sclk ampp, ampm v ih2 =0v k00?3, k10, k20?3 with pull-down sin, sclk v ih3 =0v p00?3, p10?3 with pull-down reset, test v il =v ss k00?3, k10, k20?3, p00?3, p10?3 sin, sclk, ampp, ampm reset, test v oh1 =0.1? ss r10, r11, r13 v oh2 =0.1? ss r00?3, r12, p00?3, p10?3 sout, sclk v ol1 =0.9? ss r10, r11, r13 v ol2 =0.9? ss r00?3, r12, p00?3, p10?3 sout, sclk v oh3 =-0.05v com0? v ol3 =v l3 +0.05v v oh4 =-0.05v seg0?7 v ol4 =v l3 +0.05v v oh5 =0.1? ss seg0?7 v ol5 =0.9? ss
14 s1c60n08/60r08 analog circuit characteristics and current consumption s1c60n08 (normal operating mode) characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a max. 1/2? l2 0.9 -1.90 3/2? l2 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 2.0 4.0 typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.0 2.2 min. 1/2? l2 - 0.1 -2.30 3/2? l2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load s1c60n08 (heavy load protection mode) characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a max. 1/2? l2 0.9 -1.90 3/2? l2 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 20 25 typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 10 12 min. 1/2? l2 - 0.1 -2.30 3/2? l2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load
15 s1c60n08/60r08 s1c60l08 (normal operating mode) characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a max. -0.95 2? l1 0.9 3? l1 0.9 -0.95 -1.00 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 100 -1.10 100 v dd -0.9 20 3 2.0 4.0 typ. -1.05 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.20 1.0 2.2 min. -1.15 2? l1 - 0.1 3? l1 - 0.1 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.45 -1.50 -1.30 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.1v v im =v ip 30mv during halt without during operation ? 2 panel load s1c60l08 (heavy load protection mode) max. -0.95 2? l1 0.85 3? l1 0.85 -0.95 -1.00 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 100 -1.10 100 v dd -0.9 20 3 10 15 typ. -1.05 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.20 6.5 8.5 min. -1.15 2? l1 - 0.1 3? l1 - 0.1 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.45 -1.50 -1.30 v ss +0.3 characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.1v v im =v ip 30mv during halt without during operation ? 2 panel load
16 s1c60n08/60r08 S1C60A08 (normal operating mode) characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a a max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 2.0 5.0 70 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.1 3.0 50 min. -1.15 2? l1 - 0.1 3? l1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load during operation at 500khz ? 2 S1C60A08 (heavy load protection mode) characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a a max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 10 15 75 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 6.5 8.5 55 min. -1.15 2? l1 - 0.1 3? l1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load during operation at 500khz ? 2
17 s1c60n08/60r08 s1c60r08 (normal operating mode) target: s1c60n08 characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a max. 1/2? l2 0.9 -1.90 3/2? l2 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 2.0 9.0 typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.0 6.5 min. 1/2? l2 - 0.1 -2.30 3/2? l2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load s1c60r08 (heavy load protection mode) target: s1c60n08 characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a max. 1/2? l2 0.9 -1.90 3/2? l2 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 10 20 typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 6.5 11.5 min. 1/2? l2 - 0.1 -2.30 3/2? l2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load
18 s1c60n08/60r08 s1c60r08 (normal operating mode) target: S1C60A08 characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a a max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 2.0 10 150 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.1 7.5 115 min. -1.15 2? l1 - 0.1 3? l1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit, sub-bld circuit and analog comparator are in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load during operation at 500khz ? 2 s1c60r08 (heavy load protection mode) target: S1C60A08 characteristic lcd drive voltage bld voltage ? 1 bld circuit response time sub-bld voltage sub-bld circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption ? 1: ? 2: (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc1 =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage, c 1 ? 5 =0.1 f) symbol v l1 v l2 v l3 v b0 v b1 v b2 v b3 v b4 v b5 v b6 v b7 t b v bs t bs v ip v im v of t amp i op unit v v v v v v v v v v v sec v sec v mv msec a a a max. -0.95 2? l1 0.9 3? l1 0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 v dd -0.9 10 3 10 20 160 typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 6.5 12.5 120 min. -1.15 2? l1 - 0.1 3? l1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 v ss +0.3 the relationships among v b0 ? b7 are v b0 >v b1 >v b2 >...v b5 >v b6 >v b7 . the bld circuit and sub-bld circuit are in the on status (hlmod="1", bls="0"). the analog comparator is in the off status. condition connect 1 m ? load resistor between v dd and v l1 (without panel load) connect 1 m ? load resistor between v dd and v l2 (without panel load) connect 1 m ? load resistor between v dd and v l3 (without panel load) blc="0" blc="1" blc="2" blc="3" blc="4" blc="5" blc="6" blc="7" non-inverted input (ampp) inverted input (ampm) v ip =-1.5v v im =v ip 15mv during halt without during operation ? 2 panel load during operation at 500khz ? 2
19 s1c60n08/60r08 oscillation characteristics oscillation characteristics will vary according to different conditions (elements used, boad pattern). use the following char- acteristics are as reference values. s1c60n08/60r08 (osc1 crystal oscillation) characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak unit v v pf ppm ppm ppm v m ? max. 5 10 -3.5 typ. 20 45 min. -1.8 -1.8 -10 35 200 condition t sta 5sec ( v ss ) t stp 10sec ( v ss ) including the parasitic capacitance inside the chip v ss =-1.8 to -3.5v c g =5 to 25pf ( v ss ) between osc1 and v dd (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: q13mc146, c g =25pf, c d =built-in, ta=25 c) s1c60l08 (osc1 crystal oscillation) characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance ? 1: symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak unit v v pf ppm ppm ppm v m ? max. 5 10 -1.7 typ. 20 45 min. -1.1 -1.1 (-0.9) ? 1 -10 35 200 parentheses indicate value for operation in heavy load protection mode. condition t sta 5sec ( v ss ) t stp 10sec ( v ss ) including the parasitic capacitance inside the chip v ss =-1.1 (-0.9) ? 1 to -1.7v c g =5 to 25pf ( v ss ) between osc1 and v dd (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: q13mc146, c g =25pf, c d =built-in, ta=25 c) S1C60A08 (osc1 crystal oscillation) characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak unit v v pf ppm ppm ppm v m ? max. 5 10 -3.5 typ. 20 45 min. -2.2 -2.2 -10 35 200 condition t sta 5sec ( v ss ) t stp 10sec ( v ss ) including the parasitic capacitance inside the chip v ss =-2.2 to -3.5v c g =5 to 25pf ( v ss ) between osc1 and v dd (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: q13mc146, c g =25pf, c d =built-in, ta=25 c) S1C60A08/60r08 (osc3 cr oscillation) characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc3 vsta t sta vstp unit % v msec v max. 30 3 typ. 480khz min. -30 -2.2 -2.2 condition (v ss ) v ss =-2.2 to -3.5v (v ss ) (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =82k ? , ta=25 c) S1C60A08/60r08 (osc3 ceramic oscillation) characteristic oscillation start voltage oscillation start time oscillation stop voltage symbol vsta t sta vstp unit v msec v max. 5 typ. min. -2.2 -2.2 condition (v ss ) v ss =-2.2 to -3.5v (v ss ) (unless otherwise specified: v dd =0v, v ss =-3.0v, ceramic oscillator: 500khz, c gc =c dc =100pf, ta=25 c)
20 s1c60n08/60r08 basic external connection diagram s1c60n08 and s1c60l08 k00 : k03 k10 k20 : k23 p00 : p03 p10 : p13 sin sout sclk ampm ampp r00 : r03 r11 (lamp) r12 (fout) seg0 seg47 com0 com3 r10 (bz) r13 (bz) cb ca v l1 v l2 v l3 v dd osc1 osc2 v s1 osc3 osc4 reset test v ss + lamp piezo c 1 c 5 n.c. 3.0 v (s1c60n08) or 1.5 v (s1c60l08) n.c. c p c gx x'tal s1c60n08 s1c60l08 lcd panel i/o sio o i x'tal c gx c 1 c 2 c 3 c 4 c 5 c p r a1 r a2 crystal oscillator trimmer capacitor capacitor capacitor capacitor capacitor capacitor capacitor protection resistor protection resistor 32.768 khz or 38.400 khz, c i = 35 k ? 5?5 pf 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3.3 f 100 ? 100 ? r13 (bz) r10 (bz) r a2 when the piezoelectric buzzer is driven directly r a1 piezo [the potential of the substrate (back of the chip) is v dd .] capacitors (c 2 ? 4 ) are connected. connection depending on power supply and lcd panel specification. note: the above tables are simply an example, and are not guaranteed to work.
21 s1c60n08/60r08 S1C60A08 k00 : k03 k10 k20 : k23 p00 : p03 p10 : p13 sin sout sclk ampm ampp r00 : r03 r11 (lamp) r12 (fout) seg0 seg47 com0 com3 r10 (bz) r13 (bz) cb ca v l1 v l2 v l3 v dd osc1 osc2 v s1 osc3 osc4 reset test v ss + lamp piezo c 1 c 5 cr c gc r cr c dc 3.0 v c p c gx x'tal S1C60A08 lcd panel i/o sio o i x'tal c gx cr c gc c dc r cr c 1 c 2 c 3 c 4 c 5 c p r a1 r a2 crystal oscillator trimmer capacitor ceramic oscillator gate capacitor drain capacitor resistor for cr oscillation capacitor capacitor capacitor capacitor capacitor capacitor protection resistor protection resistor 32.768 khz or 38.400 khz, c i = 35 k ? 5?5 pf 500 khz 100 pf 100 pf 82 k ? 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3.3 f 100 ? 100 ? r13 (bz) r10 (bz) r a2 when the piezoelectric buzzer is driven directly r a1 piezo ? 1 ? 1 ceramic oscillation ? 2 cr oscillation ? 2 [the potential of the substrate (back of the chip) is vdd.] capacitors (c 2 ? 4 ) are connected. connection depending on power supply and lcd panel specification. note: the above tables are simply an example, and are not guaranteed to work.
22 s1c60n08/60r08 s1c60r08 (target for s1c60n08) k00 : k03 k10 k20 : k23 p00 : p03 p10 : p13 sin sout sclk otprst ampm ampp r11 (lamp) r12 (fout) seg0 seg47 com0 com3 r10 (bz) r13 (bz) cb ca v l1 v l2 v l3 v dd osc1 osc2 v s1 osc3 osc4 reset test v ss + lamp piezo c 1 c 5 n.c. n.c. c p c gx x'tal s1c60r08 lcd panel 3.0 v i/o sio i x'tal c gx c 1 c 2 c 3 c 4 c 5 c p r a1 r a2 ic1 crystal oscillator trimmer capacitor capacitor capacitor capacitor capacitor capacitor capacitor protection resistor protection resistor serial eeprom 32.768 khz or 38.400 khz 5?5 pf 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3.3 f 100 ? 100 ? ? r13 (bz) r10 (bz) r a2 r a1 piezo errout scl sda a0 a1 a2 v ss v cc nc scl sda ic1 when the piezoelectric buzzer is driven directly ? : see "serial eeprom" [the potential of the substrate (back of the chip) is vdd.] capacitors (c 2 ? 4 ) are connected. connection depending on power supply and lcd panel specification. note: the above tables are simply an example, and are not guaranteed to work.
23 s1c60n08/60r08 s1c60r08 (target for S1C60A08) k00 : k03 k10 k20 : k23 p00 : p03 p10 : p13 sin sout sclk otprst ampm ampp seg0 seg47 com0 com3 cb ca v l1 v l2 v l3 v dd osc1 osc2 v s1 osc3 osc4 reset test v ss + c 1 c 5 cr c gc r cr c dc 3.0 v c p c gx x'tal s1c60r08 lcd panel i/o sio i r13 (bz) r10 (bz) r a2 r a1 piezo ? 1 ? 1 ceramic oscillation ? 2 cr oscillation ? 2 r11 (lamp) r12 (fout) r10 (bz) r13 (bz) lamp piezo errout scl sda a0 a1 a2 v ss v cc nc scl sda ic1 x'tal c gx cr c gc c dc r cr c 1 c 2 c 3 c 4 c 5 c p r a1 r a2 ic1 crystal oscillator trimmer capacitor ceramic oscillator gate capacitor drain capacitor resistor for cr oscillation capacitor capacitor capacitor capacitor capacitor capacitor protection resistor protection resistor serial eeprom 32.768 khz or 38.400 khz 5?5 pf 500 khz 100 pf 100 pf 82 k ? 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3.3 f 100 ? 100 ? ? when the piezoelectric buzzer is driven directly ? : see "serial eeprom" [the potential of the substrate (back of the chip) is vdd.] capacitors (c 2 ? 4 ) are connected. connection depending on power supply and lcd panel specification. note: the above tables are simply an example, and are not guaranteed to work.
24 s1c60n08/60r08 package plastic qfp5-100pin 20 0.1 25.6 0.4 51 80 14 0.1 19.6 0.4 31 50 index 0.3 0.1 30 1 100 81 2.7 0.1 0.26 3.4 max 2.8 1.5 0 12 0.15 0.05 0.65 plastic qfp15-100pin 14 0.1 16 0.4 51 75 14 0.1 16 0.4 26 50 index 0.18 25 1 100 76 1.4 0.1 0.1 1.7 max 1 0.5 0.2 0 10 0.125 0.5 +0.1 ?.05 +0.05 ?.025 unit: mm
25 s1c60n08/60r08 pad layout s1c60n08/60l08/60a08 diagram of pad layout x (0, 0) die no. y 3.73 mm 3.74 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 chip thickness: 400 ? pad opening: 95 ? s1c60n08/60l08/60a08 pad coordinates no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pad name ampp ampm k23 k22 k21 k20 k10 k03 k02 k01 k00 sin sout sclk p03 p02 p01 p00 p13 p12 p11 p10 r03 r02 r01 r00 r12 r11 r10 r13 v ss reset x 1,294 1,164 1,034 904 774 644 514 384 254 124 -7 -137 -267 -397 -527 -657 -787 -917 -1,048 -1,178 -1,308 -1,438 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 y 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,686 1,556 1,426 1,296 1,166 1,036 812 682 457 327 no. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pad name osc4 * osc3 * v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb com3 com2 com1 com0 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 x -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,415 -1,285 -1,155 -1,025 -895 -765 -635 -505 -375 -245 -115 15 145 275 405 535 665 y 176 46 -84 -214 -344 -503 -633 -763 -893 -1,022 -1,153 -1,283 -1,413 -1,543 -1,673 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 no. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 pad name seg30 seg29 seg28 seg27 seg26 seg25 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 x 795 925 1,055 1,185 1,315 1,445 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 y -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,621 -1,465 -1,310 -1,180 -1,050 -920 -790 -660 -530 -400 -270 -140 -10 120 250 380 510 640 770 900 1,030 1,160 1,290 1,420 1,550 1,680 unit: m ? : S1C60A08 only
26 s1c60n08/60r08 s1c60r08 diagram of pad layout y x (0, 0) 7.00 mm 8.35 mm 1 5 10 15 20 25 die no. 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 chip thickness: 400 ? pad opening: 95 ? s1c60r08 pad coordinates no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pad name ampp ampm k23 k22 k21 k20 k10 k03 k02 k01 k00 sin sout otprst sclk p03 p02 p01 p00 scl sda p13 p12 p11 p10 r03 r02 r01 r00 r12 r11 r10 r13 v ss x 2,893 2,638 2,382 2,127 1,871 1,616 1,360 1,105 849 594 339 83 -85 -260 -438 -683 -863 -1,064 -1,275 -1,566 -1,821 -2,126 -2,405 -2,685 -2,978 -3,686 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 y 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,090 2,787 2,657 2,527 2,288 2,064 1,599 1,470 no. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 pad name rest osc4 osc3 v s1 osc2 osc1 v dd v l3 v l2 v l1 ca cb errout com3 com2 com1 com0 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 x -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -3,420 -3,116 -2,811 -2,507 -2,203 -1,899 -1,595 -1,290 -986 -682 -378 -74 230 534 838 1,142 1,446 y 1,340 733 517 300 -576 -793 -958 -1,174 -1,391 -1,607 -1,824 -2,040 -2,241 -2,429 -2,645 -2,862 -3,088 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 no. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pad name seg30 seg29 seg28 seg27 seg26 seg25 seg24 test seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 x 1,751 2,055 2,359 2,663 2,967 3,272 3,661 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 y -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,049 -2,590 -2,355 -2,119 -1,883 -1,647 -1,411 -1,175 -939 -703 -467 -231 4 240 476 712 948 1,184 1,420 1,656 1,892 2,128 2,364 2,600 2,836 unit: m
27 s1c60n08/60r08 this page is blank.
s1c60n08/60r08 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2001 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department europe & u.s.a. 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department asia 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ epson electronic devices website issue august, 2001 printed in japan l

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